module test01;

	// Inputs
	reg Ir_Write;
	reg PC_Write;
	reg clk_im;
	reg clk_n;
	reg clk_25M;

	// Outputs
	wire [4:0] rs1;
	wire [4:0] rs2;
	wire [4:0] rd;
	wire [3:0] AN;
	wire [7:0] seg;
	wire [6:0] opcode;
	wire [2:0] funct3;
	wire [6:0] funct7;

	// Instantiate the Unit Under Test (UUT)
	main uut (
		.Ir_Write(Ir_Write), 
		.PC_Write(PC_Write), 
		.clk_im(clk_im), 
		.clk_n(clk_n), 
		.clk_25M(clk_25M), 
		.rs1(rs1), 
		.rs2(rs2), 
		.rd(rd), 
		.AN(AN), 
		.seg(seg), 
		.opcode(opcode), 
		.funct3(funct3), 
		.funct7(funct7)
	);

	initial begin
		// Initialize Inputs
		Ir_Write = 0;
		PC_Write = 0;
		clk_im = 0;
		clk_n = 0;
		clk_25M = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		Ir_Write=1;
		PC_Write=1;
		#100
		clk_im = 1;
		#20
		clk_im = 0;
		#100
		clk_im = 1;
		#20
		clk_im = 0;
		#100
		clk_im = 1;
		#20
		clk_im = 0;
		#100
		clk_im = 1;
		#20
		clk_im = 0;
		#100
		clk_im = 1;
		#20
		clk_im = 0;
		#100
		clk_im = 1;
		#20
		clk_im = 0;
		#100
		clk_im = 1;
		#20
		clk_im = 0;
		#100
		clk_im = 1;
		#20
		clk_im = 0;
	end
	
	initial begin
		forever #1 clk_25M=~clk_25M;	
	end
      
endmodule

